1. Field of the Invention
The invention relates to a receiver circuit, and more particularly to a receiver circuit of a memory device that dynamically adjusts duty cycle of various input signal voltages or external voltages to the memory device for generating output signals having a 50% duty cycle.
2. Description of the Related Art
Double data rate synchronous dynamic random access memory (DDR SDRAM) is a class of memory integrated circuits used in computers. Compared to single data rate (SDR) SDRAMs, the DDR SDRAM interface provides higher data transfer rates through stricter control of the timing of electrical data and clock signals. Implementations of such timing control frequently utilize technologies such as phase locked loop (PLL) and self-calibration to reach the required timing accuracy. The interface uses double pumping technique, i.e., transferring data on both the rising and falling edges of a clock signal, to lower clock frequency. One advantage of keeping the clock frequency low is that it reduces signal integrity requirements on the circuit board connecting the memory to the controller. The name “double data rate” refers to the fact that a DDR SDRAM with a certain clock frequency achieves nearly twice the bandwidth of a single data rate (SDR) SDRAM running at the same clock frequency, due to the double pumping technique.
For a DDR SDRAM, it is important that the memory device provides a 50% stable duty cycle, e.g., as measured by the positive or negative pulse width, for certain critical signals, such as clock and strobe signals, especially when it is operating in a high frequencies environment. However, due to the design nature of a receiver, especially in a current mode logic (CML) receiver, the duty cycle is dependent upon the power and reference voltages provided to the memory device. Any change in the external voltage, internal voltage or reference voltage, will cause the duty cycle to change.
Therefore, a novel receiver circuit that is capable of dynamically adjusting a duty cycle of an input signal to compensate for changes in external voltages, internal voltages or reference voltages and providing an output signal having a 50% duty cycle is highly required.